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Apparatus and method of drilling in multilayer semiconductor package Method for semiconductor laser drilling

IP.com Disclosure Number: IPCOM000083114D
Publication Date: 2005-Mar-01
Document File: 8 page(s) / 204K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multilayer laser drilling. Benefits include improved functionality, improved reliability, process simplification, improved design flexibility, improved throughput time (TPT), and improved yield.

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Apparatus and method of drilling in multilayer semiconductor package Method for semiconductor laser drilling

Disclosed is a method for multilayer laser drilling. Benefits include improved functionality, improved reliability, process simplification, improved design flexibility, improved throughput time (TPT), and improved yield.

Background

      One of the greatest challenges to substrate manufacturing is routing more trace features through tighter spatial constraints. One design option is to route electrical traces through multiple substrate layers by using stacked microvias structure. Two drawbacks to stacked microvias are their reliability under thermal stressing and performance under current mobile and desktop requirements.

      Conventionally, the most cost effective via drilling process utilizes CO2 laser drilling. For identical via size per layer, the total number of microvia laser-drilling steps equals the number of layers. Each build-up layer requires a via-to-land interface (see Figure 1).

      Two microvia sizes on the same layer are not currently utilized due to the TPT impact and via-to-pad alignment deterioration. Drilling multiple via sizes can only be accomplished conventionally using two separate via formation processes and two separate machines. Essentially, the pattern for one via dimension is fully processed through the laser equipment with the optimized settings for the required size. The panel is processed through a secondary laser equipment set with a patterning program for another via dimension. The panel proceeds to the next processing step. Using two separate machines requires the panel to be transferred from the first laser drill unit to the following one, doubling the time for aligning and drilling the panel. Additionally, misalignment due to machine-to-machine variability occurs.

      Some specific applications, such as coreless package technology, benefit from the capability to drill various via sizes in the same layer, particularly for the top layer and the controlled collapse chip collect (C4) vias.

              Coreless packages have stacked via structures to provide the shortest path for power and signal delivery across the package. Stacked-via reliability typically determines package reliability and robustness. Stacked-via failure in a coreless package is conventionally a critical concern. Fabricating a reliable stacked via structure is vital for coreless technology (see Figure 2).

      Experimental data indicates that stacked-via failure is mainly via delamination at the via bottom interface with a strong correlation to misalignment. Misaligned stacks have a higher failure rate compared to stacks with better alignment. A misaligned stack introduces additional stresses on its components. A better aligned via stack with fewer interfaces improves the over all reliability of the package. Figure 3 illustrates this impact. Here the misalignment contribution, designated as D1, is comprise...