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Method for a through silicon via interconnect application on WB silicon

IP.com Disclosure Number: IPCOM000083119D
Publication Date: 2005-Feb-28
Document File: 3 page(s) / 50K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a through silicon via interconnect application on wirebond (WB) silicon. Benefits include improved functionality, improved performance, and improved design flexibility.

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Method for a through silicon via interconnect application on WB silicon

Disclosed is a method for a through silicon via interconnect application on wirebond (WB) silicon. Benefits include improved functionality, improved performance, and improved design flexibility.

Background

              Conventionally, in 8x5 and 8x6 application processors, the functionality and high speeds of these devices are driving increased input/output (I/O) requirements. More integrated power and ground die pads are required at the die level. Wire-bond pads are utilized for power and ground connections at a 2:1:1 or 4:1:1 ratio. For every 2 signals, 1 power and 1 ground are required on the die pad ring, which eliminates 33% of the available die pads for signals. To compensate, the silicon size increases so all I/O, power, and ground pads fit into the die perimeter. Multiple bonding shelves with additional loop heights cannot be used due to extremely thin mold cap and overall vertical heights. Silicon functional blocks are removed to decrease the size, resulting in a loss of functionality for customers (see Figure 1).

General description

      The disclosed method uses of through silicon vias (TSVs) to distribute signals on a wire-bonded die to the side opposite the wire-bond die pads. Critical die-pad ring space is available for increasing I/O counts.

              The key elements of the disclosed method include:

•             TSVs to redistribute signals to the die-side opposite of the wire-bond die pads

•             Consecutive signal pad distribution on silicon

•             Combination of flip chip (FC) and WB interconnection within a single piece of silicon

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to enabling a smalle...