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Method of wafer-level underfill for copper bump technology

IP.com Disclosure Number: IPCOM000083120D
Publication Date: 2005-Feb-28
Document File: 5 page(s) / 121K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for wafer-level underfill for copper bump technology. Benefits include improved functionality, reliability, design flexibility, throughput time, and process simplicity.

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Method of wafer-level underfill for copper bump technology

Disclosed is a method for wafer-level underfill for copper bump technology. Benefits include improved functionality, reliability, design flexibility, throughput time, and  process simplicity.

Background

              Conventional underfill processes use capillary flow to dispense underfill material between the die and the substrate. This process places severe limitations on minimum bump pitch, bump pattern, and minimum gap height between die and substrate, which are essential for future generations of microprocessors. The capillary underfill process limits the material set, reduces the process window, and is prone to voiding. This process limits throughput time (TPT) and is expensive due to single die process.

              Conventionally, underfill process issues are solved by extensive material and process optimization, which must be performed for every bump pattern.

              Conventional controlled collapse chip collect (C4) assembly steps include the following:

1. Electroplate copper bumps on silicon, using a thick photoresist layer to define the bumps (see Figure 1). Silicon wafer is singulated into dice.

2.           Screen-print solder on the package with a solder resist mask. Die and package are jointed together by reflow the solder.

3. Dispense underfill and cure after the chip-joint process (see Figure 2).

              Under-fill voiding is related to the material flow property, die size, chip gap, and die bump pattern.

General description

      The disclosed method uses a spin-on under-fill precursor on a silicon wafer to serve as resist material for copper bump electroless plating. The under-fill precursor is fully cured at the chip-joint process step during assembly.

              The key elements of the disclosed method include:

•             Under-fill material as a part of the silicon wafer processing, which eliminates the requirement for epoxy capillary underfill process in assembly and restrictions on bump pitch, bump diameter, and gap height

•             Tailoring of the bump pitch, diameter and bump height to reduce stress on the dielectric in the die

•             Solder screen printing on the package, using the conventional process

•             Optimized gap between the solder and solder resist mask on the substrate so the die bump exactly fits into the opening to enable suitable chip joining without voiding

•             Underfill cure during the chip-joint process

Advantages

              The disclosed method provides advantages, which includes,
•             Improved functionality due to enabling bump depopulation, which is crucial to high speed and analog products
•             Improved performance due to optimizing the bump height and diameter

•             Improved reliability due to preventing underfill voiding issues

•             Improved reliability due to reducing stress on low-k dielectric without capillary flow limitations

•             Improved reliability due to redu...