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Universal Secondary Interconnect Component for Test Interface Boards

IP.com Disclosure Number: IPCOM000083148D
Publication Date: 2005-Mar-01
Document File: 3 page(s) / 173K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a universal interconnect (i.e. for the connection between the space transformer and the tester interface mother board) that matches the standardized pitch and accommodates the largest substrate sizes.

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Universal Secondary Interconnect Component for Test Interface Boards

Disclosed is a method for a universal interconnect (i.e. for the connection between the space transformer and the tester interface mother board) that matches the standardized pitch and accommodates the largest substrate sizes.

Background

To accommodate various package sizes, a customized interconnect is typically created by a supplier to match the substrate size. In addition, the interconnect requires customized mechanical hardware to support the new form factor. Together, these items inhibit cost reduction opportunities, increase probe card integration complexity, and increase overall lead-time.

For current wafer level testing, a customized space transformer substrate is used to maintain a fixed pattern and size (see Figure 1). With the fixed layout and substrate size, suppliers provide a matching interconnect solution that remains the same for multiple products. This allows for a single mechanical hardware design from the supplier to integrate the space transformer, regardless of product type. However, due to the low volume and complexity of the space transformer device, the component is very costly.

General Description

The disclosed method uses a universal interconnect to match the standardized pitch (or land pad-to-pad spacing) and accommodate the largest substrate size for variable packages used for various products. The disclosed method also enables card suppliers to standardize their hardware to reduce costs and allow for a common interface design to address stiffness and alignment requirements.

The disclosed method modifies the probe card’s mechanical hardware to handle the various sizes and number of land pads already designed by the product teams. In addition, the disclosed method enables wafer level testing with lower cost probe cards.

Figure 2 is an example of t...