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Method for an IHS with an optimized cavity construction

IP.com Disclosure Number: IPCOM000083160D
Publication Date: 2005-Mar-01
Document File: 6 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an integrated heatsink (IHS) with an optimized cavity construction. Benefits include improved functionality, improved performance, and improved power performance, improved reliability, and reduced cost effectiveness.

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Method for an IHS with an optimized cavity construction

Disclosed is a method for an integrated heatsink (IHS) with an optimized cavity construction. Benefits include improved functionality, improved performance, and improved power performance, improved reliability, and reduced cost effectiveness.

Background

      Conventional processor packages have a limited cavity space for a large die or multiple dice underneath the integrated heatsink (IHS).

      A typical thermal stack includes the following (see Figure 1):
•             Package
•             Die

•             Thermal interface material (TIM)

•             IHS

      Conventional thermal stacks including the following (see Figure 2):

•             Package

•             Die

•             TIM

•             IHS

•             Epoxy

•             IHS sealant

      Space for dice and other components is limited under the IHS due to the wide step that is required for mechanical stability.

      To adequately remove heat, the inner height of the IHS and the thickness of the TIM must be carefully designed. A poor thermal path results in poor thermal performance or failure of the microprocessor.

      A stacked package includes two or more dice in one package. If significant thickness variation exists between two or more dice, the lack of a robust thermal path for heat removal can result in poor performance or die failure (see Figure 3).

      Thermal stacks must have the correct load distribution from an IHS to the package with an adequate bond-line thickness (BLT) at the thermal interface. The load transfer is particularly important for assemblies with high compressive retention loads and/or low stiffness, such as in thin or coreless electronic packages. 

              Load transfer through multiple dice is not conventionally identified as an issue. As a result, no solution has been identified for low stiffness packages and/or high compressive retention loads.

              A cross-section of a typical multiprocessor package with an IHS has a sustained compressive load applied to the top of the IHS into the package. For a land-grid array (LGA) socket, the compressive load may be substantial, >100 lbs (see Figure 4). The retention solution that applies a sustained compressive load on top of the IHS to create an electrical connection between the package and a LGA socket is not depicted.

General description

              The disclosed method is an IHS with an optimized cavity construction. The method includes an internal cavity construction that is staggered or slanted. Alternatively, the IHS can have multiple inner heights for packages containing multiple dice with different thickness. In another variation, the electronic package can incorporate a center post or posts to set the BLT for the TIM and/or improve the load distribution from the IHS to the package.

              The key elements of the disclosed method include:

•             Cavity construction that is staggered or slanted...