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Process for Photolithographic Alignment

IP.com Disclosure Number: IPCOM000083186D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Gegenwarth, RE: AUTHOR [+2]

Abstract

In fabricating large-scale integrated circuits some process operations require two layers of photoresist, for example, to prevent pinholes. With such heavy layers, or with composite layers of pyrolytic oxide and nitrides which are only semitransparent, the equipment presently used for aligning photomasks is unsatisfactory in certain instances.

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Process for Photolithographic Alignment

In fabricating large-scale integrated circuits some process operations require two layers of photoresist, for example, to prevent pinholes. With such heavy layers, or with composite layers of pyrolytic oxide and nitrides which are only semitransparent, the equipment presently used for aligning photomasks is unsatisfactory in certain instances.

A method is described for improving the visibility of alignment marks upon wafers, when aligning photomasks over thick photoresist with monochromatic light.

A deep crevice, several microns in depth, is etched into the wafer substrate area at or prior to the first masking step performed in the process. Such a crevice has been found to be visible throughout all processing steps by presently utilized printing systems. Accordingly, all alignments made after the first masking operation becomes secondary alignments, in the sense that the A level mask is aligned with the crevice and the B level mask is aligned with the same mark, etc.

In one preferred mode, such a crevice can be formed by reactive ion etching on the substrate which produces extremely sharp walls having little edge bias. The described method reduces rework and improves yield and reliability, due to better and more actuate alignment.

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