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Signal Monitoring and Control Circuit for Semiconductor Device Test Probe

IP.com Disclosure Number: IPCOM000083190D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Creveling, VL: AUTHOR [+2]

Abstract

This semiconductor device test probe protection system, permits selection of one of several sources of test power for a given test probe; controls the application of power to the probe so that the level of power is raised to a desired level in a controlled interval, to permit slow charging of capacitive filters associated with the probe; and, thereafter, causes power to be removed from the probe quickly, in the event that an overcurrent condition occurs.

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Signal Monitoring and Control Circuit for Semiconductor Device Test Probe

This semiconductor device test probe protection system, permits selection of one of several sources of test power for a given test probe; controls the application of power to the probe so that the level of power is raised to a desired level in a controlled interval, to permit slow charging of capacitive filters associated with the probe; and, thereafter, causes power to be removed from the probe quickly, in the event that an overcurrent condition occurs.

The source selection circuitry in Fig. 1 generally consists of a field-effect transistor (FET) switch array, designed to permit selection of one of four sources of power for a given test channel.

The power sequence circuits of Fig. 2, on command, apply power to the probe slowly raising the level of power from zero to a desired output level in a predetermined interval. The sequence circuits each generally consist of an integrator and an operational amplifier driving an FET, designed to function as a voltage-variable resistor.

Upon occurrence of a "power up" signal, the integrater produces a ramp voltage which is applied to the operational amplifier input causing its output to move with the ramp voltage, whereby the resistance of the FET is controlled to increasingly apply the desired level of power to the selected power channel.

The system otherwise includes a pair of comparator circuits illustrated in Fig. 3, associated with each power chan...