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Electrical Contact Through an SiO(2) Overlay by Ultrasonic Probe

IP.com Disclosure Number: IPCOM000083200D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Schick, JD: AUTHOR

Abstract

Failure analysis of semiconductors having SiO(2) overlays cannot be completely performed, without electrical probing of aluminum lines under the overlay. This technique allows such probing and also aluminum line isolation.

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Electrical Contact Through an SiO(2) Overlay by Ultrasonic Probe

Failure analysis of semiconductors having SiO(2) overlays cannot be completely performed, without electrical probing of aluminum lines under the overlay. This technique allows such probing and also aluminum line isolation.

By mounting a tungsten probe tip vertically in the horn of an ultrasonic wire bonder in place of the bonding tip, electrical contact can be made to aluminum lines under the SiO(2) overlay. The tungsten tip should have the smallest radius possible (0.25 mil) but larger are permissible.

The chip is positioned under the ultrasonically driven tip which is lowered to just above the line to be contacted. Another contact is made elsewhere on the chip through a device on the same line using another probe. These two probes, ultrasonic tip and stationary probe, are connected to a curve tracer and a bias voltage is applied.

The ultrasonically driven probe is slowly lowered with the ultrasonic power on, while the operator observes the trace. Low-ultrasonic power to match the new tuning of the tungsten tip is used; and as soon as the probe reaches the line, the curve tracer indicates contact. At this point the power is turned off, and testing can be carried out in situ or the chip can be removed and probed at another test station.

The ultrasonically driven probe tip does no damage to the adjacent area of the chip at these low powers. Larger contact holes can be made and the smallest, depending...