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Overvoltage Protection for Driver Circuits

IP.com Disclosure Number: IPCOM000083201D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Bodendorf, DJ: AUTHOR [+3]

Abstract

These circuits feature detectors which sense the onset of avalanche breakdown and clamp the drivers in a safe mode, thereby eliminating the possibility of damage to the circuit due to the excessive currents.

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Overvoltage Protection for Driver Circuits

These circuits feature detectors which sense the onset of avalanche breakdown and clamp the drivers in a safe mode, thereby eliminating the possibility of damage to the circuit due to the excessive currents.

The transistors in the driver circuits have a lower avalanching threshold than the normal supply voltage needed for interface drivers. A lower voltage cannot be used because of a larger voltage output requirement of the circuit to be driven, such as a field-effect transistor (FET) circuit. Both circuits use an open-base sensing transistor to detect the overvoltage condition, and to set the output stages into a BV(cer) instead of a BV(ceo) condition. It is well-known that in a group of similar transistors, the one with an absolutely open base avalanches before the remainder.

In Fig. 1, the emitter of open-base device Q20 is directly connected to the negative terminal of the power supply. The positive terminal of the supply (ground) is connected to the collector of Q20 through a series resistor R1 and diode Q19, which prevents Q20 from avalanching under normal working conditions. Additional Schottky barrier or PN junction diodes mav be added in series with Rl, if the power supply -VH is larger. Node A is the output terminal of the avalanche detector.

The control circuitry consists of diodes Q21, Q22 and Q23, all of which are driven by node A. They are normally off during normal operation of the driver. When an overvoltage condition causes node A to become highly negative, Q22 pulls down the ENABLE control line at the base of the device Q4 whereby Q4 and Q5 are turned off, thereby permitting current switch transistors Q3-Q6 to respond to the data input which is held down by Q21. As a result, the collector of Q6 becomes positive and that of Q3 becomes negative, irrespective of the logical states of the signals applied at the DATA and the ENABLE inputs. The ENABLE control of the circuit is of the open collector type (not shown in Fig. 1).

The outputs from the collectors of Q3 and Q6 are fed to the bases of Q13 and Q14 via D...