Browse Prior Art Database

Low Power FET Storage Cell

IP.com Disclosure Number: IPCOM000083227D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Linton, RH: AUTHOR [+3]

Abstract

Load devices Q3 and Q4 of a field-effect transistor (FET) storage cell can be biased below their threshold level, so as to reduce the current supplied to the storage cells to a minimum.

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Low Power FET Storage Cell

Load devices Q3 and Q4 of a field-effect transistor (FET) storage cell can be biased below their threshold level, so as to reduce the current supplied to the storage cells to a minimum.

Devices Q1 and Q2 are cross-coupled FET's which store a bit of information. The bit of information stored depends on whether Q1 or Q2 is conducting. While the circuit is not being addressed for reading or writing information, Q1 and Q2 are powered by source V through load devices Q3 and Q4. This power is the minimum level necessary to maintain the state of the bistable circuit. That is, the amount of power supplied to the bistable circuit is sufficient to permit nondestructive reading of the information stored in the cell.

The power supplied is maintained at this minimum level by connecting the gates of devices Q3 and Q4 back to their sources. This biases these devices below their threshold level which is supposed to bias devices Q3 and Q4 off. However in fact a small trickle current still passes through the devices so biased, as shown by the experimental curve of drawing B. This trickle current is sufficient to maintain the states stored in the bistable circuit.

Additional power is supplied to the bistable circuit from the bit lines B1 and B0, when the voltage on the word line is energized to render devices Q5 and Q6 conductive. With increased power supplied through devices Q5 and Q6, reading and writing functions may be performed by addressing the word...