Browse Prior Art Database

MOSFET Associative Cell

IP.com Disclosure Number: IPCOM000083228D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Linton, RH: AUTHOR [+2]

Abstract

The connection between gates of the load devices 10 and 12 and the bit lines 14 and 16, enables this 6-device storage cell to be used for associative memory purposes.

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MOSFET Associative Cell

The connection between gates of the load devices 10 and 12 and the bit lines 14 and 16, enables this 6-device storage cell to be used for associative memory purposes.

In the quiescent state of the storage cell the bit lines 14 and 16 and the associative sense line 28 are at a positive potential, while the word line 22 is at a ground potential. While in this quiescent state, information is stored in the cell by the conduction of either field-effect transistor (FET) 18 or FET 20. With FET 18 on and FET 20 off a "0" is stored in the cell, and with FET 20 on and FET 18 off a "1" is stored in the cell.

To read the information stored in the storage cell, the word line 22 is taken from ground to some positive potential turning FET's 24 and 26 on, so that the current on the bit lines 14 and 16 is representative of the potentials at nodes A and B, respectively.

To change the information stored in the storage cell, either bit line 14 or 16 is brought to ground potential while simultaneously taking the word line 22 to some positive potential. If a 1 is to be written into the storage cell bit line 16 is brought to ground, and if a 0 is to be written bit line 14 is brought to ground potential.

An associative search operation is performed by grounding one bit line 14 or 16, while the other remains in its quiescent level and sensing the current on the associative sense line 28. Only a word having a match in each bit location would have zero current in th...