Browse Prior Art Database

Four Device FET Cell Regeneration Method

IP.com Disclosure Number: IPCOM000083229D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Kumar, VR: AUTHOR [+2]

Abstract

This field-effect transistor (FET) storage cell's word line 10 is powered at three different levels to enable higher performance.

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Four Device FET Cell Regeneration Method

This field-effect transistor (FET) storage cell's word line 10 is powered at three different levels to enable higher performance.

Reductions in power dissipation are obtained in storage cells by storing the data as charge in the interelectrode capacitances C1 and C2 of cross-connected FET devices Q1 and Q2, and intermittently recharging the capacitances through the bit lines 12, 14 and FET devices Q3 and Q4. Normally, the number of storage cells that can be regenerated at one time is small, because the high impedances of the diffused bit lines 12 and 14 causes high-voltage drops. resulting in loss of data when a large number of cells are regenerated at one time.

To increase the number of storage cells that can be regenerated at once, a third level voltage can be supplied to the word line 10 for addressing the cell for such regeneration operations. Thus the word line 10 is energized at any one of three levels: a high level (+6 volts) for use during the reading or writing of information from the cell, a low level (ground level) for maintaining the storage cell isolated from the bit lines 12 and 14, and an intermediate level (+4 volts) for use when the storage cell is addressed for regeneration of the charge on capacitors C1 and C2.

This intermediate level maintains the devices Q3 and Q4 at a higher impedance than the high level does during a normal reading or writing cycle. Thus the current that passes from the cells to the...