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Clock for Data Processing Apparatus

IP.com Disclosure Number: IPCOM000083238D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Bish, JJ: AUTHOR

Abstract

An oscillator 2, a shift register 3, and associated components produce a sequence of timing pulses T1, T2, T3, T4 selectively in response to controlling signals. An AND gate 4 responds to the output of oscillator 2 at one input and to a delayed oscillator output at the other input, to produce a series of pulses of a selected width at an input to advance shift register 3.

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Clock for Data Processing Apparatus

An oscillator 2, a shift register 3, and associated components produce a sequence of timing pulses T1, T2, T3, T4 selectively in response to controlling signals. An AND gate 4 responds to the output of oscillator 2 at one input and to a delayed oscillator output at the other input, to produce a series of pulses of a selected width at an input to advance shift register 3.

An AND gate 6 responds to controlling signals to load a 1 bit into the first stage of shift register 3. When a single 1 bit is loaded into register 3, register 3 produces a sequence of four timing pulses without regard to the state of gate 6.

AND gate 6 has a controlling input 7 that selects the circuit of the drawing or deselects this circuit, so that a different timing circuit can be selected. An input 8 is controlled by an associated processor to start and stop the clock, or an alternative input 9 stops the clock after a counter, not shown, counts a selected number of timing pulses.

Latches 11 and 12 and an AND gate 13 produce an input 14 to control gate
6. Latches 11 and 12 form a 2-bit counter that counts through the sequence 00, 01, 10, 11 on each sequence of four pulses from oscillator 2. AND gate 13 operates as a decoder that produces a pulse on line 14 for each fourth pulse from oscillator 2, when the count in latches 11 and 12 is 11. Thus, when the controlling signals on lines 7, 8 and 9 are at a 1 logic level, a signal on line 14 opens gate 6 to ente...