Browse Prior Art Database

Extended Control for Microprocessors

IP.com Disclosure Number: IPCOM000083274D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Smith, PF: AUTHOR

Abstract

With reference to Fig. 1, the large rectangular area control store 1 corresponds to the rectangular control store array used in conventional designs to store control information. Fig. 1 shows a cross-hatched region labelled unoccupied control store 2 where physical hardware is absent. If the cross-hatched area 2 is included and the block labelled field steer gating 3 is omitted, this is a conventional microprocessor configuration.

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Extended Control for Microprocessors

With reference to Fig. 1, the large rectangular area control store 1 corresponds to the rectangular control store array used in conventional designs to store control information. Fig. 1 shows a cross-hatched region labelled unoccupied control store 2 where physical hardware is absent. If the cross- hatched area 2 is included and the block labelled field steer gating 3 is omitted, this is a conventional microprocessor configuration.

By providing the additional hardware of the steering circuitry and accepting a small increment of time delay in that circuitry, a significant saving in control store bits is realized, while retaining the much more powerful control functions of a long-word machine. The benefits of a long-word design (fewer full-machine cycles to achieve a useful function) are realized at the cost of some circuit delay in the shift network. In other words, the output register 4 in Fig. 1 "sees" a 32-bit control word presented to it by the control store 1, where the region covered by the shifter circuitry (field steer gating 3) appears to be 24 bits long rather than the actual 16 bits shown.

It is assumed that the software assembler cr compiler, which would be used by a practical design would assign operations requiring the full simultaneous function of the 24-bit or 32-bit region to only the region of control store where full physical storage is provided. In practical designs, such assignments can be given to powerful, often-used, subroutines, while more general code can be assigned higher in memory where storage is saved by the use of this method.

Fig. 1 shows only those functions related to access and decode of control words.

Consider that a control store word is to be accessed and that its address has been placed in control store address register 5. Some part of that address invokes the shifting function (i.e., an address higher than some limit set by the design). See the line control from address dependency 6. When the addressed word comes out of the control store 16, the operation field (always present) is taken into the operation register 7 and decoded in decoder 8.

The operation always implies which control fields from the virtual 24-bit control word are nulls. The operation code field can then establish the field shifting to properly align the control fields into the 24 output register 4 for final decoding 10. The operation code provides the shift control.

If the three control store fields in the example align directly with the desired position in the output register 4, no shift is required and each bit from each of the three fields gates directly to the corresponding bit position in the output register
4.

Fig. 2 illustrates the shift control lines, C (11,12) and the data lines 13,14,15 to the instruction register...