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Bit Line Latch Gating Circuit for Field Effect Transistor Memory

IP.com Disclosure Number: IPCOM000083289D
Original Publication Date: 1974-Oct-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

This circuit sections a memory array into two halves while using a pair of cross-coupled bit line latches. The bit line latches include transistors 5, 6, 7 and 8.

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Bit Line Latch Gating Circuit for Field Effect Transistor Memory

This circuit sections a memory array into two halves while using a pair of cross-coupled bit line latches. The bit line latches include transistors 5, 6, 7 and
8.

It is well known in the state of the art, that cross-coupled bit line latches can be used as a circuit amplifier for the cell sense current in field-effect transistor (FET) memory arrays. Typically, the latches are triggered once per cycle and will discharge the bit line corresponding to the down node of the selected cell.

However, when the array is sectioned in two halves for improved performance with a shorter bit line time constant, the bit lines on the two halves of the array have to be isolated from each other, if every pair of sectioned bit lines are to have their own cross-coupled latches. This is necessary due to the fact that once triggered, the latches will set in one state or the other depending on either the selected cell polarity or noise on the bit lines.

Since only one side of the array can have the selected cell, the bit line pair without the selected cell has to be isolated from the common bit lines. This takes redundant bit decoding which uses up chip area.

To overcome this problem, the cross-coupled latches are gated with a decoder-like circuit including transistors 9-16 and 17-24, one such circuit for each half of the memory array. The SARX or SARX inputs denote the highest ordered storage address register (SAR), which...