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Transparent Read Cycle for Nonvolatile Memory

IP.com Disclosure Number: IPCOM000083342D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Kenyon, RA: AUTHOR [+3]

Abstract

This system enables the improvement in performance of slow-write/fast-read memory technologies, such as nonvolatile MXOS memories. An integrated circuit chip architecture is described which enables a slow write cycle to be interrupted by a read request. It is assumed that previous knowledge of MXOS technology is known, and that memory programming is achieved by a series of short pulses which may be interrupted without disturbing the write process.

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Transparent Read Cycle for Nonvolatile Memory

This system enables the improvement in performance of slow-write/fast-read memory technologies, such as nonvolatile MXOS memories. An integrated circuit chip architecture is described which enables a slow write cycle to be interrupted by a read request. It is assumed that previous knowledge of MXOS technology is known, and that memory programming is achieved by a series of short pulses which may be interrupted without disturbing the write process.

A WRITE cycle includes an erase and an imprint operation. During the erase operation, all data bits of a selected word are set to a low-threshold voltage. During an imprint operation, data is written by changing the threshold of selected bits to a high state. The operation of the memory system is implemented as follows:

1. Write with no interrupt. Assuming the chip is in the quiescent state, latch L1 is reset (RL = 1). When a WRITE REQUEST WR is received latch L1 is set and signal WL allows the address SA to be stored in storage address register SAR1, and subsequently presented to the decoders. Latch L2 is set to indicate the write status WS and L3 enables the decode signals SD while inhibiting READ signal RD, and L5 is set to gate the data from the data bus into the input buffer.

At the end of the decode L3 is reset and the WRlTE DELAYED WD signal is transmitted to the JK flip-flop FF1. FF1 enables the write counter and the ERASE and IMPRINT signals ERS and IMP from the write counter decoder. ERS is applied to the word and bit driver control so long as FF1 is in the 1 state. This allows the correct number of negative pulses to be applied to erase the word.

When the required number of pulses is detected, the word and bit driver control is switched over to imprint mode and the data which was gated into the input buffer by WD is imprinted. When the imprint cycle is over FF1, L1, L2, L3 and L5 are reset by the END OF WRITE pulse EW....