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Field Effect Transistor Driver Circuit

IP.com Disclosure Number: IPCOM000083346D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR [+2]

Abstract

In certain field-effect transistor (FET) circuits it is necessary to limit the maximum allowable drain-to-source voltage (V/DS) for a given gate-to-source voltage (V/GS).

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Field Effect Transistor Driver Circuit

In certain field-effect transistor (FET) circuits it is necessary to limit the maximum allowable drain-to-source voltage (V/DS) for a given gate-to-source voltage (V/GS).

Fig. 1 is a schematic circuit diagram of a driver circuit capable of providing an output (Vout) of VH minus the threshold of device T2. T1 and T2 are equivalent to a single device having a length-to-width ratio of 75/1, with a driven gate area of a 150/1 device. T1 lowers the V/DS of T2 by one threshold drop (Vth), allowing both T1 and T2 to be within the maximum allowable constraints. The gate of T2 is driven by a bootstrapped inverter, T3-TS.

Fig. 2 is a schematic of a driver circuit having a 33 percent improvement in performance, with only one half the total driven gate area. The circuit operates as follows. Node A is initially charged to VH-Vth by T5 with node B subsequently rising to Vh-2Vth. The VH supply is split between T1 and T2 limiting V/DS of each device to the design restrictions.

When Vin drops, turning off T4, nodes A and C rise simultaneously to their final values. Node D approaches VH, as node B reaches VH due to the overdrive provided by node A on T1. T1, therefore, is no longer limiting the charging of the load. Effectively, T2 is the only limiting device and allows the circuit to appear as a 100/1 device, whose drain is at VH and has a total driven gate area of a 150/1 device.

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