Browse Prior Art Database

Dynamic NAND Circuit Using Inversion Layer Capacitor

IP.com Disclosure Number: IPCOM000083347D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR [+3]

Abstract

This metal-oxide semiconductor field-effect transistor (MOSFET) circuit eliminates a capacitive coupling problem caused by the floating gate of a dynamic NAND logic gate.

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Dynamic NAND Circuit Using Inversion Layer Capacitor

This metal-oxide semiconductor field-effect transistor (MOSFET) circuit eliminates a capacitive coupling problem caused by the floating gate of a dynamic NAND logic gate.

In a conventional two input dynamic NAND gate two series connected MOSFET's are used to selectively discharge an output node, which has been precharged by a precharge pulse P via transistor T5.

Referring to the circuit schematic, if it is assumed that device T4 is not present and that a logical "I" (positive voltage for N-channel devices) is applied at IN1 through isolation device T3 to the gate of T1, and if, subsequently, a logical 1 is applied to input IN2, causing T3 to turn on, node B will fall and be coupled to the gate of T1 by the channel capacitance Cch of T1. This negative going pulse on the gate of T1 will be detrimental to circuit performance.

By adding a voltage sensitive, or inversion layer, capacitor Cin in the form of transistor T4 between node A and IN2, a positive going signal on IN2 will cause node A to rise when node B is falling and will couple sufficient charge back to node A to compensate for charge lost through Cch. Device T4 may be a conventional MOSFET having its source and drain shorted.

If the sequence of input signals is reversed such that IN2 rises prior to IN1 no coupling will occur through Cin, as the gate of T4 will not be charged.

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