Browse Prior Art Database

Vertical Random Access Memory

IP.com Disclosure Number: IPCOM000083349D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR [+2]

Abstract

This semiconductor random-access memory array includes vertical charge storage memory cells, in which writing is accomplished by utilizing a punch-through condition without forward biasing an epitaxial junction. Reading is accomplished by using storage sites located in an isolated diffusion pocket as a multigated junction field-effect transistor (FET). Data is retained using zero bias voltages.

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Vertical Random Access Memory

This semiconductor random-access memory array includes vertical charge storage memory cells, in which writing is accomplished by utilizing a punch- through condition without forward biasing an epitaxial junction. Reading is accomplished by using storage sites located in an isolated diffusion pocket as a multigated junction field-effect transistor (FET). Data is retained using zero bias voltages.

Fig. 1 shows a plan view of the memory array formed on a semiconductor substrate 10. Vertically aligned word lines W/L cross horizontally aligned bit sense lines B/S, to form a plurality of storage sites in diffusion pockets 14. Fig. 2 is a vertical cross section through a bit-sense line of the array. A thin P-type epitaxial layer 12 is grown on N+ substrate 10. N+ diffusion pockets (DP) 14 are diffused or ion implanted into epitaxial layer 12, to form a plurality of storage sites.

Each diffusion pocket is covered by a thin oxide, not shown, and a metal, or polycrystalline silicon, line 16. The metal lines form word lines W/L. Contact is made at the two ends of diffusion pocket 12 to form a multigate junction FET. Oxide isolation 18 is provided for interbit sense line isolation and interstorage site isolation.

Still referring to Fig. 2, the memory array operates in the following manner.

1. Holding information. All W/L, B/S and substrate voltages are zero. Information is considered to be a logical "1" if DP 14 has a positive voltage, for example, 5 volts, and a logical "0" if DP 14 is at grou...