Browse Prior Art Database

Four Device Static Enhancement/Depletion Memory Array Cell

IP.com Disclosure Number: IPCOM000083370D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+5]

Abstract

Certain known static field-effect transistor (FET) storage cells have required six FET devices to provide for the storage and I/O gating functions. The use of depletion-type (VT < 0) FET devices allows the functions of the load and I/O devices to be combined, reducing the device count to four. Refer to Fig. 1. Normal Standby Operation (Fig. 1A) Word Line (WL) low (0V), Bit Lines (BLL and BLR) high (+5V), Depletion FET's D in low conductance state supplying current to enhancement type (VT > 0) FET's E in flip-flop. Read Cycle (Fig. 1B) Word Line WL high (+5V), FET's D in high conductance state, state of flip-flop determined by sensing current in either the left or right bit line (BLL or BLR). Write Cycle (Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 2

Four Device Static Enhancement/Depletion Memory Array Cell

Certain known static field-effect transistor (FET) storage cells have required six FET devices to provide for the storage and I/O gating functions. The use of depletion-type (VT < 0) FET devices allows the functions of the load and I/O devices to be combined, reducing the device count to four. Refer to Fig. 1. Normal Standby Operation (Fig. 1A) Word Line (WL) low (0V), Bit Lines (BLL and BLR)

high (+5V), Depletion FET's D in low

conductance state supplying current to

enhancement type (VT > 0) FET's E in flip-flop.

Read Cycle (Fig. 1B) Word Line WL high (+5V), FET's D in

high conductance state, state of flip-flop

determined by sensing current in either the

left or right bit line (BLL or BLR).

Write Cycle (Fig. 1C) Word Line WL high (+5V), either BLL or

BLR in low state (0V), setting the flip-flop.

The key to successful operation of the cell (Fig. 2) is to insure that a sufficiently large sense signal appears on the bit line, when a cell is interrogated, to override the worst possible combinations of cell charging currents. That is, IR > (N-1) IC=ICT, where IR is the reading sense current, N is the number of cells on a bit line, and IC is the charging current for each cell. This can be directly accomplished by keeping N sufficiently small or by keeping the ratio IR/IC sufficiently large. The ratio IR/IC=2 (Vgr-VTH-VDS/2)VDS/(Vgc-VTH)/2/ is determined by the change in transconductance of the I/O transistor w...