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Integrated Schottky Diode Transistor Design and Layout

IP.com Disclosure Number: IPCOM000083373D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+4]

Abstract

High-speed logic circuit design involves a trade off of noise margin and speed. The following device layout technique can be used to achieve a low VCE requirement for collector drive circuits and at the same time eliminate deep saturation of the transistor, minimizing any storage time delay penalty.

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Integrated Schottky Diode Transistor Design and Layout

High-speed logic circuit design involves a trade off of noise margin and speed. The following device layout technique can be used to achieve a low VCE requirement for collector drive circuits and at the same time eliminate deep saturation of the transistor, minimizing any storage time delay penalty.

Fig. 1 illustrates a conventional transistor utilizing a split contact Schottky diode, along with the simplified equivalent circuit.

Fig. 2 illustrates an improved design, whereupon the base is moved adjacent to the collector contact and a split base-Schottky contact is utilized. This technique bypasses an appreciable portion of the normal bulk collector resistance.

Fig. 3 illustrates an alternative approach with an additional base contact, which is not connected to the normal base input contact. In this case a controllable resistance is put in series with the Schottky diode, increasing the equivalent Schottky voltage and achieving a lower VCE.

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