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Level Shifted Emitter Coupled Logic

IP.com Disclosure Number: IPCOM000083375D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Nestwork, WJ: AUTHOR [+2]

Abstract

An improved emitter followerless emitter-coupled logic (ECL) circuit is illustrated in Fig. 1. A "T" resistor is utilized to shift down the signal level since regardless of the logical input level, a constant current flows in RD. This allows optimization of both signal swing and diode clamping action.

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Level Shifted Emitter Coupled Logic

An improved emitter followerless emitter-coupled logic (ECL) circuit is illustrated in Fig. 1. A "T" resistor is utilized to shift down the signal level since regardless of the logical input level, a constant current flows in RD. This allows optimization of both signal swing and diode clamping action.

In a common clamped ECL circuit, the diode forward drop determines the signal swing, thus the signal swing is larger than would be necessary for optimum speed and noise considerations. Also, it should be noted that the uplevel is independent of the diode anode voltage. Thus, even with a high forward drop diode there is no danger of saturation of the input transistor of the next stage.

If a large voltage swing is desired for special applications of off-chip drivers, it can be developed using the signal levels from Fig. 1 to drive the circuit in Fig. 2.

This circuit offers a significant advantage over more conventional ECL approaches which utilize emitter-follower outputs. Since the emitter-follower consumes considerable power, its elimination places the level shifted (LS) ECL circuit at a power dissipation which is similar to high speed T/2/L circuits, while still retaining many of the advantages of ECL circuit configurations.

Another feature of the circuit which is not shown is the possible use of a forward biased Schottky diode to supply VR. This eliminates the need for a separate VR voltage supply.

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