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Synchronous Frequency Division by 2.5

IP.com Disclosure Number: IPCOM000083394D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Karabatsos, C: AUTHOR [+2]

Abstract

Frequency division by a noninteger is not a common function. The divider shown in Fig. 1 accomplishes a frequency division by 2.5.

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Synchronous Frequency Division by 2.5

Frequency division by a noninteger is not a common function. The divider shown in Fig. 1 accomplishes a frequency division by 2.5.

The divider consists of two, two-bit counters, and an auxiliary latch which controls the oscillator input polarity by which all latches in the circuit are clocked. Latches C and B are part of one two-bit counter and latches C and A are part of the other two-bit counter. Latch L is common to both counters. All latches are D- edge triggers. That is, the inputs D are transferred to the outputs Q at clock time.

The divider operates as follows: The first two positive going edges of the oscillator pulses operate counter latches C and B. During the third positive going edge of the oscillator pulse, latches L and C are turned on. The output of the L latch conditions the oscillator input gates. Latch C at this time is part of the counter formed by latches C and A.

While the L latch is on, the negative going edges of the oscillator pulses will stop the counter latches C and A. When L latch turns off again, the positive going oscillator pulse edge will take control to step the appropriate counter latches and the process will repeat.

The period of the oscillator output is equal to 2.5 periods of the input oscillator. The boolean expression for the oscillator output is QcQbQa QaQc. Synchronous division is accomplished by simultaneously clocking all the latches.

Waveforms at the output of the latches are shown...