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High Speed Parallel To Serial Data Translation

IP.com Disclosure Number: IPCOM000083400D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Adams, FV: AUTHOR [+2]

Abstract

Parallel-to-serial data translation may be performed at a higher rate and use less storage volume, by (1) eliminating the pause in a serial data string during parallel data transfer, and (2) masking consecutive register loads against preceding register loads and storing the address of any bits that are different.

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High Speed Parallel To Serial Data Translation

Parallel-to-serial data translation may be performed at a higher rate and use less storage volume, by (1) eliminating the pause in a serial data string during parallel data transfer, and (2) masking consecutive register loads against preceding register loads and storing the address of any bits that are different.

Fig. 1 shows apparatus for eliminating the pause in a serial data string during parallel data transfer. A CPU transfers data by word into a register 12 through a switch 14. An address generator 16 specifies the location of the words in register 12 as directed by control logic 18. Once the data is loaded into the register 12, it is transferred to a register 20 for a serial delivery except for the first two bits of word 1. The control logic 18 causes bits 1 and 2, in sequence, to be transmitted to an output line 22 through gates 24 and 26. Data from the register 20 is transmitted through gate 28 to the output line 22, as directed by the control logic
18.

As soon as shifting starts from the register 20, new data is loaded into the register 12 and the cycle repeated. No pause exists between successive loading and unloading of register 12 by reason of transmitting the first 2 bits of the first word to the output, as the remaining bits and words in register 12 are unloaded for serial transmission from register 20.

Fig. 2 shows a further speed enhancement for parallel-to-serial data transmission. A compare gate 30...