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Monolithic Storage Cell Having Inherent Latent Image Memory Operation

IP.com Disclosure Number: IPCOM000083401D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+2]

Abstract

The difference in capacitances for metal lines and diffusion lines in semiconductors may be utilized to achieve latent image memory operation.

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Monolithic Storage Cell Having Inherent Latent Image Memory Operation

The difference in capacitances for metal lines and diffusion lines in semiconductors may be utilized to achieve latent image memory operation.

Fig. 1 shows a standard 6-device cell comprising transfer devices A and F; load devices B and D and storage devices C and E. Fig. 2 shows a topological layout for the storage cell of Fig. 1. Metallization 10 extends from node 2 to the gate of storage device E.

A diffusion connection extends from node 1 to node 3 or the gate of device C.

The diffusion line has ten times the capacitance and four hundred times the resistance of the metal line 10. The metal interconnect 10 allows the storage device E to turn on first. The cell is referred to as a left (L) or node 2 "high" memory. A right (R) or node 1 "high" memory can be achieved by mere imaging the layout.

The transfer devices A and F are directly attached to bit lines 1 and 0, respectively. The direct connection yields the lowest possible resistance which maximized read and write times for the storage cell. The cell power dissipation is determined by the load devices B and D.

As the load devices are lengthened, their internal resistance increases and power is reduced. The bit lines and transfer devices A and F remain fixed. The active devices may also be expanded linearly to improve read time. However as the read time is improved the write time is reduced.

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