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Selective Edge Triggered Pulse Generator Circuit

IP.com Disclosure Number: IPCOM000083402D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Myers, MJ: AUTHOR

Abstract

Described is a selective edge triggered pulse generator circuit, which reduces the number of externally provided control signals necessary for its operation.

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Selective Edge Triggered Pulse Generator Circuit

Described is a selective edge triggered pulse generator circuit, which reduces the number of externally provided control signals necessary for its operation.

Fig. 1 outlines two externally provided, nonoverlapping periodic control or clock signals A and B and a resultant third periodic signal C. The described circuit creates a signal C during the nonoverlap time between signals A and B. The circuit of Fig. 2 has the flexibility of producing signal C after A falls and before B rises or after B falls and before A rises, while maintaining the same periodicity as A and B.

With both A and B at a low level and no voltage stored on capacitor C, the output node will be at a high level. As signal A rises, transistor Q1 will conduct current and charge capacitor C, thereby causing Q3 to turn on and the output will be pulled to a low-voltage level.

When signal A falls and B remains at a low level the stored charge on C will hold Q3 on and maintain a low-output level. As signal B rises, Q4 is turned on to maintain the low-output level and Q2 is turned on to remove the stored charge from C. When B falls, Q4 is turned off allowing Q5 to drive the output to a high- voltage level. The output will remain high until A rises causing Q1 and Q3 to conduct, thereby returning the output node to a low level.

The value of capacitor C must be large enough to store the charge required to keep Q3 conducting during the A to B nonoverlap time. T...