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High Impedance Strobed Level Detector

IP.com Disclosure Number: IPCOM000083403D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Davis, JW: AUTHOR [+2]

Abstract

Described is a circuit for detecting time and voltage related occurrences at the output of a field-effect transistor (FET) circuit. The circuit was designed to provide both high accuracy in the time domain and a high-input impedance.

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High Impedance Strobed Level Detector

Described is a circuit for detecting time and voltage related occurrences at the output of a field-effect transistor (FET) circuit. The circuit was designed to provide both high accuracy in the time domain and a high-input impedance.

Fig. 1A represents a presently accepted technique for performing voltage limit comparison gated by time. Digital-to-analog converter (DAC) 1 is controlled to establish a DC level on the positive terminal of operational amplifier 2. The amplifier will switch when the negative terminal, output from the device under test (DVT), exceeds the DC reference. Output of the amplifier is converted at 3 to a logic signal, which is ANDED with the output of pulse generator 4 to set trigger 5 indicating an error; i.e., the DUT output occurred too late in time, was not of sufficient amplitude, or did not switch.

Implementation requires an amplifier with good AC characteristics and which is relatively insensitive to slope variations from the DUT. Such amplifiers typically exhibit low-input impedance (less than 10K ohm) which can not be driven by many FET circuits.

The circuit of Fig. 2A improves upon that in Fig. 1A by combining time and voltage references into a single event, whereby the time transition is constant and fast relative to the DUT output. This single event is then the controlling input to the amplifier 9, negating time differences caused by variations in the DUT output. This allows the use of amplif...