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Interleaved Control Store Buffer

IP.com Disclosure Number: IPCOM000083406D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Pedersen, RJ: AUTHOR

Abstract

For topological reasons, high-density large-scale integration (LSI) arrays are designed with a built-in hierarchy with respect to the address lines. There is usually a row address, which addresses some multiple of the final output data width, and a "bit" address to do the final selection. This bit address is usually a considerably faster address path through the array.

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Interleaved Control Store Buffer

For topological reasons, high-density large-scale integration (LSI) arrays are designed with a built-in hierarchy with respect to the address lines. There is usually a row address, which addresses some multiple of the final output data width, and a "bit" address to do the final selection. This bit address is usually a considerably faster address path through the array.

Two identical buffers A/B of arbitrary size are built with these array chips as shown. This scheme is intended for use as a fully associative high-speed control store buffer. The control register contains a next address field (NA), and a pointer to the next microinstruction in the microprogram. The NA field includes ~ bit address which accesses both arrays directly and simultaneously. The A/B bit gates the desired buffer's output into the control register. These two fields represent the fast access (one cycle) address path.

The remaining portion of the NA field gets translated through a directory 1 into a row address and is loaded into either or both of the row address registers 2, 3. The number of bits in this subfield determines the unit of associativity, i.e., the size of the directory. Now the bit pattern in the row address registers 2, 3 points to a subset of the buffer, and a fast access can be made within this subset via the bit address and A/B select subfields of the next address.

Changing the contents of the row address registers 2, 3 is controlled by order...