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Programmable Logic Array One Cycle Split Adder

IP.com Disclosure Number: IPCOM000083408D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Brickman, NF: AUTHOR [+2]

Abstract

An approach is presented for the implementation of an eight or sixteen-bit single-cycle adder in Programmable Logic Arrays (PLAs), which results in an efficient compression of function into the available hardware. An extension to larger size adders would be straightforward.

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Programmable Logic Array One Cycle Split Adder

An approach is presented for the implementation of an eight or sixteen-bit single-cycle adder in Programmable Logic Arrays (PLAs), which results in an efficient compression of function into the available hardware. An extension to larger size adders would be straightforward.

The PLAs have 2-bit decoders 10 supplying inputs to the AND array 12 and 2-bit exclusive ORs 14 at the outputs of the OR array 16. There is assumed to be an ORing capability (dotted or otherwise) on the PLA outputs 18.

The adder is split up into two or more contiguous bit-groups for implementation into the PLA, according to the splitting that provides best efficiency for the chip hardware at hand. To each higher order bit group is added a carry-in and a not carry-in generator. The addition result for the higher order bit positions is then generated twice (in the exclusive OR array), once for the case of there being a carry-in and once for there being no carry-in. The results of the carry-in (or not carry-in) generation is then used to mask (set to 0) the incorrect addition result in the exclusive OR array.

Fig. 2 shows the adder, implemented in three 4-bit sections. The low-order 4 bits carry-generate are handled in the conventional manner (lines 9-18). The symbol-pair UU denotes the exclusive OR operation, and PP denotes the OR.

In Fig. 2, the carry-generate for the high-order 4 bits is replicated twice: once assuming a carry-in of 0 from the low...