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Level Sensitive Logic Testing Method

IP.com Disclosure Number: IPCOM000083422D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Tatak, VH: AUTHOR [+2]

Abstract

The primary inputs and outputs of logic to be tested are connected to Stable Shift Register Latches (SSRL's), whereby there is one path into and out of the logic assembly. The SSRL's are part of the tester and are connected in series. This arrangement is represented in Fig. 1.

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Level Sensitive Logic Testing Method

The primary inputs and outputs of logic to be tested are connected to Stable Shift Register Latches (SSRL's), whereby there is one path into and out of the logic assembly. The SSRL's are part of the tester and are connected in series. This arrangement is represented in Fig. 1.

Shift register 10, Fig. 2, loaded in parallel functions to scan patterns into the logic assembly 15 under test. The output patterns from assembly 15 enter shift register 20 and are looked at in parallel by compare register 25, with expected result patterns entered into register 30. The scanned out pattern can also be fed back into input register 10 via loop control 35.

This arrangement provides data reduction becase all patterns are of one format. Test time is efficient, in that the test patterns and expected results are loaded in parallel and the comparison takes place in parallel. The test arrangement is relatively inexpensive, because of the simple shift register interfaces on the inputs and outputs.

Current state of the art tester architectures use the single input change principle. That is for each primary input force value (1 bit), the pin address (EG 8 bits for a 256 pin tester) for that value must also be provided and included in the test data. The same is true for expected outputs. However, with the described SSRL arrangement address data need not be explicitly carried in the test data, because it is implicit in the physical sequence of the pin...