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Extended Character Set for Matrix Printers or Displays

IP.com Disclosure Number: IPCOM000083425D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 5 page(s) / 131K

Publishing Venue

IBM

Related People

Check, GP: AUTHOR [+3]

Abstract

Control circuitry for buffered matrix printers or displays includes the combination of a random-access memory (RAM) and read-only storage (ROS) for economically extending the printable or displayable character set. Character generation data for a normal set of characters is contained in ROS which is accessed by first accessing RAM. Character generation data for extended characters, i.e., characters which may vary according to needs of different countries or purposes, is contained in RAM. This character generation data is obtained by accessing the RAM a second time where the second RAM access address is obtained from ROS.

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Extended Character Set for Matrix Printers or Displays

Control circuitry for buffered matrix printers or displays includes the combination of a random-access memory (RAM) and read-only storage (ROS) for economically extending the printable or displayable character set. Character generation data for a normal set of characters is contained in ROS which is accessed by first accessing RAM. Character generation data for extended characters, i.e., characters which may vary according to needs of different countries or purposes, is contained in RAM. This character generation data is obtained by accessing the RAM a second time where the second RAM access address is obtained from ROS.

The RAM serves the dual function of buffering the character data and character generation data for the extended characters. The RAM 10, Fig. 1B, is initially addressed by an address formed from 8 bits furnished by a print head position (character position) counter, not shown, and from a high/low selection HI/LO SEL bit. The first access of RAM 10 is always made with the HI/LO SEL bit at the low condition. The 8-bit address from the print head position counter is passed by gate 13, Fig. 1A, via OR circuit 17 and bus 18 to address register (MAR) 19. A HI/LO address signal is passed by OR circuit 60 to provide a SEL HI/LO ADD bit on line 66 to RAM 10, Fig. 1B. A 1st RAM access signal generated by timing control logic, not shown, but occurring as seen in Fig. 2, is passed by OR circuit 61, Fig. 1A, as select signal SEL.

The data to be read from RAM 10 had previously been entered therein via bus 11 which also provided addresses to MAR 19 via gate 12. OR circuit 17 and bus 18. RAM 10 is either in a read or a write mode and it is assumed to be in the read mode after it has been loaded via bus 11.

During the first RAM access, the character retrieved from RAM 10, Fig. 1B, is used as an address together with bits from a print emitter column counter, not shown, for addressing ROS 25. The 8 bits retrieved from RAM 10 are present on bus 21 and are applied to RAM byte gate 29, controlled by a SEL RAM BYTE signal from OR circuit 41. The two high-order bits, bits 0 and 1, of these 8 bits are applied to AND circuit 33. Additionally bit 0 is applied to inverters 42 and 44 and to AND circuit 37. Bit 1 is also applied to AND circuits 34 and 36 and to inverter 45.

Inverters 42 and 43 feed AND circuit 34 and inverters 44 and 45 feed AND circuits 36 and 37, respectively. AND circuits 33, 34 and 36 and 37 are conditioned by a signal from AND circuit 46 which receives 1st RAM ACC, not WTC/ASCII and not RAM WIRE MODE signals. AND circuit 33 and 34 feed OR circuit 35 to provide a SEL ROS LOW BYTE signal for conditioning ROS LOW BYTE gate 30. AND circuits 36 and 37 feed OR circuit 38, to provide a SEL ROS HI BYTE signal for conditioning ROS HIGH BYTE gate 31. Gates 30 and 31 will be further described after a ROS access has been described.

RAM BYTE gate 29 is conditioned only if AND circu...