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Variable Performance Processors

IP.com Disclosure Number: IPCOM000083435D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Igel, JJ: AUTHOR

Abstract

A range of data processors is provided by a bus structure arrangement where three internal buses can be operated as a single bus, three independent buses or in any combination of two or three by gating control, which consists of three AND-OR circuit arrangements. This arrangement enables the number of bus usages to be changed, and thereby change the performance of the processor to provide a range or family of processors.

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Variable Performance Processors

A range of data processors is provided by a bus structure arrangement where three internal buses can be operated as a single bus, three independent buses or in any combination of two or three by gating control, which consists of three AND-OR circuit arrangements. This arrangement enables the number of bus usages to be changed, and thereby change the performance of the processor to provide a range or family of processors.

The performance of the processor is also changed by changing the utilization of the arithmetic and logic unit (ALU) by a wider control word. This arrangement for providing a range of processors is particularly advantageous for computer systems utilizing large-scale integration (LSI) technology. Extensive hardware changes to provide a range of processors is eliminated, and when LSI technology is involved, this represents a considerable cost savings.

A data flow diagram for the processors is shown in Fig. 1. The three buses are the A, B and C buses which for a minimum performance processor are all connected together as a unitary bidirectional bus.

The connections are made by AND-OR circuit gates A0-A, A0-B and A0-C. The details for these gates is shown in Fig. 2.

The gates enable each of the buses A, B and C to be electrically isolated from each other or to be logically connected to each other. Bus A can be logically connected to bus B by activating AND circuits A3 and A4. This allows bus A to be gated through OR's 0...