Browse Prior Art Database

Digital Compensating Read System

IP.com Disclosure Number: IPCOM000083436D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+3]

Abstract

This read system maintains a switching threshold for the outputs of phototransistors 10 and 12 activated, respectively, by light-emitting diodes (LED's) 14 and 16, depending upon the position of holes 18, 19 in a document card 20. The switching threshold is nearly a constant percentage of the maximum signal from each phototransistor 10 and 12 with the card 20 being removed, regardless of absolute signal values from the phototransistors; and this is accomplished using a digital memory 22 and a means for setting a threshold value in the memory 22.

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Digital Compensating Read System

This read system maintains a switching threshold for the outputs of phototransistors 10 and 12 activated, respectively, by light-emitting diodes (LED's) 14 and 16, depending upon the position of holes 18, 19 in a document card 20. The switching threshold is nearly a constant percentage of the maximum signal from each phototransistor 10 and 12 with the card 20 being removed, regardless of absolute signal values from the phototransistors; and this is accomplished using a digital memory 22 and a means for setting a threshold value in the memory 22.

The LED 14 and phototransistor 10 form a first channel, and the LED 16 and phototransistor 12 form a second channel. Channels 1 and 2 are time division multiplexed on a common output signal line 24 driving log amplifier 25 by multiplex drivers 26, included in control logic 28.

The system has two modes, namely, calibrate and read. Control logic 28 includes switch 30 which causes the system to be in calibrate mode when switch 30 is open, and causes the system to be in read mode when switch 30 is closed. In read mode, document card 20 is moved between the LEDs 14 and 16 and phototransistors 10 and 12, so that the card holes 18 are between the LED 14 and phototransistor 10 and the holes 19 are between the LED 16 and the phototransistor 12. In calibrate mode, card 20 is removed completely from between the LEDs 14 and 16 and phototransistors 10 and 12.

In calibrate mode, with switch 30 being open, a digital value is set in memory 22 which determines the threshold used by each of the channels 1 and 2 while reading. This is done as follows: Channel 1 is selected by turning on its LID 14, using drivers 26, and is allowed to stabilize, producing a constant output from phototransistor 10 on output line 24, Log amplifier 25 having line 24 as its input, thus produces a constant output on its output line 32 applied to comparator 34.

The input to the digital-analog converter (DAC) 36 is varied with successively increasing digital values in memory 22, until the output from converter 36 on line 38 applied to comparator 34 is approximately equal to the offset output voltage from the log amplifier 25, as determined by comparator 34. This digital value is then stored in memory 22 for use during the read cycle.

Channel 2 is then selected using the multiplexing drivers 26, and the corresponding digital value for channel 2 is also stored in memory 22 for use during the read cycle. Memory 22 is controlled by data bus 40, addressing bus 42 and read/write line 44, all of which are output; of control logic 28. Control logic 28 is controlled by the output of comparator 34 on line 46.

When all channels have thus been calibrated, the system is switched to read mode by closing switch 30. This has the effect of providing a greater voltage to the LEDs, increasing the intensity of illumination from the LEDs. The document card 20...