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Memory Address Checking Technique

IP.com Disclosure Number: IPCOM000083450D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Hodges, P: AUTHOR

Abstract

A simple check on address input lines and address decoding logic is accomplished, by combining the parity bit of the address with the parity bit of the data.

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Memory Address Checking Technique

A simple check on address input lines and address decoding logic is accomplished, by combining the parity bit of the address with the parity bit of the data.

The data and address is received from the memory address register 1 and applied to address decode logic circuit 2. The data with parity is in storage 3, which receives the address signal. An exclusive OR logic circuit 4 is used to check for an anticipated odd number of binary 1's in a nine-bit word, for example.

The data bytes and addresses are generated with odd parity, and the data byte parity bit is exclusive ORed with the address parity bit during writing or reading. Thus, bytes stored in memory locations whose addresses have an even number of 1's (0, 3, 5, 7, 9) are stored with even parity, and bytes stored in other memory locations are stored with odd parity.

A single error in generating a memory address will produce an incorrect address parity, which will in turn produce incorrect parity in the output data obtained from data register 5. In this way, errors in the address are detected at only one point.

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