Browse Prior Art Database

Instruction Bit Efficiency in Microprogrammed Digital Computers

IP.com Disclosure Number: IPCOM000083451D
Original Publication Date: 1975-May-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Related People

Langdon, GG: AUTHOR

Abstract

Minimizing the bit dimensions of instruction words in microprogrammed digital computers, increases the power of a given instruction size and enables a reduction in memory size. Contemporary instructions use several bits to select the proper address pointer. As described subsequently, the information defining the function to be performed by the instruction is itself used to select the proper addressing pointer of a pair of pointers when the address pointers are normally selected individually. This is achieved by associating a (possibly nonexistent) predetermined field of the instruction with the type or class of instruction.

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Instruction Bit Efficiency in Microprogrammed Digital Computers

Minimizing the bit dimensions of instruction words in microprogrammed digital computers, increases the power of a given instruction size and enables a reduction in memory size. Contemporary instructions use several bits to select the proper address pointer. As described subsequently, the information defining the function to be performed by the instruction is itself used to select the proper addressing pointer of a pair of pointers when the address pointers are normally selected individually. This is achieved by associating a (possibly nonexistent) predetermined field of the instruction with the type or class of instruction.

The specific embodiment of this description is a microprocessor, driven by compact instructions. As such, the bits-per-instruction is kept small. A single address instruction is used, where one operand is an accumulator register AR, and the other is indicated by an address field in the instruction. In the prior art, for example in the IBM S/360 Model 25 internal instruction (or "control word" as it was called), a field in the control word that determined which of eight "pointer" registers will be used as an address to reference storage was employed. In the case of the Model 25, the control word field is 3 bits, and the address itself is 16 bits. Furthermore, the 16-bit address used may be incremented or decremented by certain amounts before being returned to the pointer register. This allows the control word program to conveniently deal with data addresses in a consecutive manner, as is the case when dealing with operands composed of a plurality of adjacent words. This incrementing or decrementing, or leaving it alone, of the address is handled by a two-bit field in the control word. (One of the features is to show how this may be done with only one control word bit.)

In moving data from one place to another in memory, two pointer register addresses are needed; one for the pointer to the data source, the other for its destination. In the S/360 Model 25 control word scheme, this is accomplished by having different addresses, one for the source, the other for the destination. In this description, a second feature groups the "pointer" registers in pairs; one register in the pair being used implicitly for the "read" or "fetch" operations and the second being used for the "write" or "store", or "ALU operation to storage" operations.

In this way, the address field need indicate only which "pair" of pointers is selected, because the Operation Code field of the instruction selects the proper pointer of the pair. For example, the S/360 Model 25 allows eight pointer registers, and when memory is accessed (either read or write) a 3-bit field in the control word specifies which pointer register. In this description, the eight pointers would be grouped into four pairs, and only a 2-bit field would be needed to specify the pair.

To exemplify an embodiment for th...