Browse Prior Art Database

Input Output Timing Control

IP.com Disclosure Number: IPCOM000083481D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Vrba, RA: AUTHOR

Abstract

Many times inexpensive memories cannot be used in a computing system due to their slowness which, depending on the systems architecture, might penalize throughput. This is obviously true where the systems clock is slowed down to accommodate the memory.

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Input Output Timing Control

Many times inexpensive memories cannot be used in a computing system due to their slowness which, depending on the systems architecture, might penalize throughput. This is obviously true where the systems clock is slowed down to accommodate the memory.

To avoid penalizing overall systems performance while at the same time using slow inexpensive memories, special memory clocking, control and architectural techniques can be employed.

Consider first the timing employed in the IBM Electronic "Selectric" Composer. Referring to Fig. 1, PHASE ONE (phi 1) is the output phase and PHASE TWO (phi 2) is the input phase; the address is outputted on phi 1 to the memory, and the data is read in on phi 2 from the memory. As can be seen, the access time is only a small fraction of the total available time. In the Electronic "Selectric" Composer asymmetrical clocks and a 6.4 microsecond cycle time are used to give the memory about 3.2 microseconds for access time.

The following method still gives the memory a 3.2 microseconds access time, but doubles the systems speed and processor throughput. This increased performance is an important feature. Secondly, symmetrical clocks are preferable in most systems, in order to perform logic decisions between each of the phases instead of just from phi 1 to phi 2. Fig. 2 shows a processor timing technique. Note that data requested at phi 1 is not inputted into the processor on the.next phi 2, but is inputted on the following phi 2. This method gives the memory a gross access time of 4.8 microseconds. Of this gross access time, 1.2 microseconds ar...