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Automatic Zero Correction Technique

IP.com Disclosure Number: IPCOM000083484D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 59K

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Boinodiris, S: AUTHOR


The usual method of calibration of a successive approximation analog-to-digital converter (ADC) involves potentiometric trimming to reduce a zero offset.

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Automatic Zero Correction Technique

The usual method of calibration of a successive approximation analog-to- digital converter (ADC) involves potentiometric trimming to reduce a zero offset.

The automatic zero correction technique described involves an automatic offset correction via a capacitive storage means. With respect to the total operating time, the converter time is separated into three sectional timings. These are a sampling period prior to the conversion followed by the conversion period, and this is followed by a post conversion sampling period until a new conversion period is initiated.

When the system is in a sampling state and therefore nonconverting, all data bits are set to an inactive state except the least-significant bit (LSB). This bit is instead sending a SAMPLE signal modulated in AND 37 by a clock signal fc. During that time, an input buffer amplifier 10, shown in a differential subtractor configuration has its input disassociated from the external source 1 by operation of switches 2 and 3, and its inputs shorted to ground through switches 4 and 5.

If Vos n is the sum of offset parameters as referred to the input of an amplifier n produced by bias currents and offset voltages, then; Vi/Sampling Period (SP) = 2 Vos 10.

Since all bits are set to an inactive state, the current source 16 indicated as Is is also off since it is driven from the decoded sign bit signal via switch 15. Then the potential at node.39, indicated as Vsj, will be modulated by a current output digital-to-analog converter 14, with a current source 12 generating current Iao pulsating with least-significant bit amplitudes.

If Reg is the equivalent resistance from node 39 to ground, then Vsj/Sampling Period = iLSB Reg + 2 Reg Vos 10/(Reg + R11 +R40). Let Reg/(Reg + R11 + R40) = k, then Vsj/SP = 2k Vos 10 + iLSB Reg.

Vsj at node 39 is now fed into an amplifier 17 of high bandwidth with offset trim capability on its first stage, with its output damped by matched diodes 18 and 19 and compensated by capacitor 20 and resistor 21. The amplifier as so connected has an input of; Ve = Vos 17 + 2k Vos 10 + iLSB (Reg/2).

The zero correction feedback loop for the amplifier 17 consists of amplifier 34 driving a differential current amplifier consisting of transistors 26, 27 and resistors 28, 29 and 30.

The current is fed into the offset adjustment points of amplifier 17 via a resistor bridge consisting of resistors 22, 23, 24 and 25. The input stage of amplifier 17 has a gain ranging between 10 and 100. The offset adjustment being at the output of the first stage sends a differential input to the output stage of amplifier 17.

The zero correction feedback loop of amplifier 17...