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Reserving Logical Address Spaces

IP.com Disclosure Number: IPCOM000083510D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 4 page(s) / 65K

Publishing Venue

IBM

Related People

Iskiyan, JL: AUTHOR [+4]

Abstract

In a multiprocessor multiported common store apparatus, each of the several CPU's X, Y, Z... can have their own independent address space for accessing the store via one or more of a plurality of Storage Access Controllers (SAC) to one or more plurality of independent storage modules 1, 2, 3, 4.... A Central Control (CC) supervises interaction of the host CPU's with the various SAC's and stores.

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Reserving Logical Address Spaces

In a multiprocessor multiported common store apparatus, each of the several CPU's X, Y, Z... can have their own independent address space for accessing the store via one or more of a plurality of Storage Access Controllers (SAC) to one or more plurality of independent storage modules 1, 2, 3, 4.... A Central Control (CC) supervises interaction of the host CPU's with the various SAC's and stores.

By wag of example, each CPU has an independent set of address spaces 0- 63, each space capable of being subdivided into three sublogical units termed pages. In the host-CPU-to-store directory, CPU-X address space 1 (1-X) has a page in each of the stores 4, 2, and 6. Each SAC connected to stores 4, 2, and 6 has address translation tables, not shown, which convert 1-X address space to real address space 4, 2, and 6.

Data stored in the various store units may be shared by a plurality of CPU's. For example, address space 2-Y and 2-Z refers to the same data signals in the store, respectively, in store units 4, 8, and 1. The sharing is indicated by the asterisks in the CPU store directory. A second address space is also shared between CPU-Y and CPU-Z in 63-Y and 1-Z being, respectively, in stores 1, 2, and 3. It is desired that any CPU can reserve unto itself any address space and the signals represented thereby as stored in stores 1, 2, 3, 4.... Since each of the SAC's can independently access a variety of the stores, each SAC must have table entries reflecting the reserve status of such logical address spaces.

If a given store is accessible by only one SAC (not shown in the drawing), then a reserve from any CPU for reserving an address space having signals therein can be reserved in accordance with known IBM 370 reserve/release procedures. On the other hand, for space shared by plural computers and when a plurality of SAC's have access to a plurality of stores which contain data in the address space to be reserved, such as address space 1-Y, then other procedures have to be followed.

The desired reserve is represented in the CPU store directory by the rectangle, with the signal storage in the stores represented by such address space indicated by the small rectangles in stores 2, 3, and 4. Each of these stores can be accessed independently by SAC's A, B, and C. Accordingly, tables in all three SAC's must have entries indicating the reserve status.

The indicated stores may be a buffer storage system with archival data being off-loaded into the store, whenever a logical address space is supplied to CC. Data represented by such logical address space need not be resident in any of the stores. Addressability (assignment of logical name) of logical address space may be established by CC with no data actually residing in any of the stores. With addressability and no data, the SAC receiving a reserve request from the given CPU responds to the reserve by entering the reserve status in CC.

A detailed description of variou...