Browse Prior Art Database

Surefire Latch

IP.com Disclosure Number: IPCOM000083521D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

In certain computer applications where error correction of digital data is done, it is desirable to have a definite output level from a data latch even if the input is at a threshold level between a logical 1 and 0. The average latch has a stable point at precisely the threshold level and could sit at the balance point for an appreciable time.

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Surefire Latch

In certain computer applications where error correction of digital data is done, it is desirable to have a definite output level from a data latch even if the input is at a threshold level between a logical 1 and 0. The average latch has a stable point at precisely the threshold level and could sit at the balance point for an appreciable time.

The latch circuit in the figure does not have such a characteristic. T1 and T2 are the latch, T3 and T4 are the input switches and T5 and T6 are the control circuit. The current I1 must be sufficient to provide a loop gain of greater than 1 when set is down. The current I2 must be large enough to switch the latch. In order for the latch to reach its balance point, two things must occur. First the latch must have begun to switch as set goes positive. Therefore, the currents in T3 and T4 must have been unbalanced at that time. This implies a second requirement to hold the latch at its balance point. The input voltage must now go to a value that balances the currents in T3 and T4, and do so in such a manner that matches the transient behavior of the latch. It is only theoretically possible for this to occur. The probability of it happening is extremely small, even when compared to the case of I1 = 0.

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