Browse Prior Art Database

Frequency Meter

IP.com Disclosure Number: IPCOM000083530D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Pezdirtz, KF: AUTHOR

Abstract

The apparatus includes a digital counter 3 having, for example, twenty stages as shown, and capable of counting pulses supplied to its input C from a clock or pulse source 5. The counter outputs are stored in a register 7, the outputs of which are supplied to an invert digital-to-analog converter (IDAC) 9. Timing single-shots 11, 13 and 15 are utilized to provide timed operating or control pulses.

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Frequency Meter

The apparatus includes a digital counter 3 having, for example, twenty stages as shown, and capable of counting pulses supplied to its input C from a clock or pulse source 5. The counter outputs are stored in a register 7, the outputs of which are supplied to an invert digital-to-analog converter (IDAC) 9. Timing single-shots 11, 13 and 15 are utilized to provide timed operating or control pulses.

In operation, assume that the counter 3 has been reset and the input data line 17 is at a logical 0.

When the line 17 transfers to a logical 1, the 4 MHz clock 5 is enabled via AND circuit 19 and the counter 3 starts to count the clock pulses. The first counter output will have a period which is twice the period of the clock. The second stage of the counter will be operating at twice the period of the first stage. This process continues until the twentieth counter position.

Because the counter outputs are running with a 50% duty cycle, a logical 1 in the first counter position represents 1/4 mu, for example. Succeeding positions of the counter 3 represent 1/2 mu, 1 mus, 2 mus, 4 mus, 8 mus, etc., up to the twentieth counter position which represents approximately 1/4 second. The output of the counter 3 at any time now represents the elapsed time, in microseconds, since the line 17 has gone to a logical 1.

On the 1-to-0 transition of line 17, two conditions occur. First, clock 5 is disabled and, after an appropriate settling time that depends upon the logic technology, the state of the counter 3 is a binary number proportion...