Browse Prior Art Database

Pedestal Clamp

IP.com Disclosure Number: IPCOM000083542D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Klara, WS: AUTHOR [+2]

Abstract

The speed of the logic circuit depicted in the drawing is enhanced by clamping the positive signal transition to an optimum level. A pedestal clamp T3, T4 is employed in conjunction with the TTL logic circuit T1, T2. SBD1, SBD2 and SBD3 are Schottky barrier diodes.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Pedestal Clamp

The speed of the logic circuit depicted in the drawing is enhanced by clamping the positive signal transition to an optimum level. A pedestal clamp T3, T4 is employed in conjunction with the TTL logic circuit T1, T2. SBD1, SBD2 and SBD3 are Schottky barrier diodes.

Transistor T4 is always conductive and produces an electrical pedestal (level shift) of approximately one Vce. This level shift is added to the forward voltage characteristic of diode-connected transistor T3 to provide the clamping level.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]