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High Sheet Resistivity Resistors by the Porous Silicon Technique

IP.com Disclosure Number: IPCOM000083556D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Poponiak, MR: AUTHOR [+2]

Abstract

This is a technique utilizing porous silicon technology to achieve an extremely large range of resistor values. This range will extend from the nominal low (10 ohms/) to extremely high (>/- 1 meg ohms/) values.

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High Sheet Resistivity Resistors by the Porous Silicon Technique

This is a technique utilizing porous silicon technology to achieve an extremely large range of resistor values. This range will extend from the nominal low (10 ohms/) to extremely high (>/- 1 meg ohms/) values.

Fig. 1 illustrates a typical resistor structure. A resistor structure is fabricated by normal diffusion or implant technology. Then a layer of porous silicon 2 is produced in the resistor structure. Contact holes 4 are made through the insulator 5 to the resistor. Porous silicon is formed by anodically biasing the silicon in an electrolyte of hydrofluoric acid and deionized water.

The porous silicon layer effectively forms a high-resistive region. Current flow is now confined to the lower part of the structure 6, thus increasing the sheet rho. Utilization of the proper starting rho and proper "depths" of porous layers, allows the achievement of an extremely large range of resistor values. Initial electrical data indicates effective resistivities have been altered from 0.01 ohm-cm to 1000 ohm-cm.

Combinations of porous depths, pore size and density and percentage porosity (air to silicon ratio) all can be varied to achieve the appropriate value resistor. Note that in Fig. 1, the porous layer does not intersect any normal P/N junctions, thus the normal leakage characteristics will not be altered. The "capping" of the porous layer is to prevent contamination or oxidation.

An alternate method for...