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Arithmetic System for Halving and Doubling Decimal Numbers

IP.com Disclosure Number: IPCOM000083558D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Chen, TC: AUTHOR [+2]

Abstract

The arithmetic system for halving or doubling a decimal number employs a plurality of logic arrays. The logic arrays are connected to receive in parallel, the bits in an input register temporarily storing a decimal number in binary-coded decimal (BCD) form. The halved or doubled output in BCD form is read out in parallel into an output register. Equal weighted wire matrix read-only memory (ROM) techniques are employed in the logic arrays, to conserve required computational hardware and to facilitate large-scale circuit integration.

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Arithmetic System for Halving and Doubling Decimal Numbers

The arithmetic system for halving or doubling a decimal number employs a plurality of logic arrays. The logic arrays are connected to receive in parallel, the bits in an input register temporarily storing a decimal number in binary-coded decimal (BCD) form. The halved or doubled output in BCD form is read out in parallel into an output register. Equal weighted wire matrix read-only memory (ROM) techniques are employed in the logic arrays, to conserve required computational hardware and to facilitate large-scale circuit integration.

In the arithmetic system for halving (Fig. 1) a halving array receives its input from two digits, but its output goes into a single digit. In the arithmetic system for doubling, the exact opposite is the case. The most significant bit output from a doubling array is a decimal carry, which constitutes the least significant bit in the next higher order digit. (This carry is not propagated).

Each logic array in the arithmetic system includes: two decoder/ drivers, a ROM matrix of column and row conductors, and switches connected to the ROM matrix for combining the output from the matrix, and generating a four-bit sequence comprising part of the output decimal number in BCD form.

Fig. 3 is a typical logic array employing current switch emitter-follower technology and represents halving array (H.A.) 3 in Fig. 1. The first decoder/driver received two bits in a sequence of four bits and provides a plurality of column outputs. The second decoder/driver receives the remaining two bits in the sequence and provides a plurality of row outputs. Each decoder/driver comprises a plurality of AND gates for providing different logical combinations of the two bits to generate the respective column and row output. Fig. 2 shows a typical logic array decoder/driver and represents the halving array decoder/driver 4, shown in Fig. 3.

A plurality of rows are divided into four identical sets and the intersection of each set of row conductors with the column conductors f...