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Producing SI Wafers without Crystal Defects

IP.com Disclosure Number: IPCOM000083572D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Biedermann, E: AUTHOR

Abstract

Into originally dislocation-free semiconductor wafers, strong slip lines are induced by thermal stresses occurring during the different high-temperature processes. These slip lines which decrease the circuit yield start on the mostly sharp-edged rectangular profile of the wafer edge, spreading into the interior of the wafer.

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Producing SI Wafers without Crystal Defects

Into originally dislocation-free semiconductor wafers, strong slip lines are induced by thermal stresses occurring during the different high-temperature processes. These slip lines which decrease the circuit yield start on the mostly sharp-edged rectangular profile of the wafer edge, spreading into the interior of the wafer.

To remedy this, the wafer is rounded along its edges by polishing or etching and is covered with an amorphous protective layer of, for example, silicon oxide, whose thickness can range from several hundred to many thousand angstrom. During the various high-temperature processes the wafer edge must be covered with this protective layer, thus suppressing the formation of undesirable slip lines.

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