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Skew Detector and Corrector for a Disk, Drum, or Tape Storage

IP.com Disclosure Number: IPCOM000083574D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR

Abstract

When clock and data pulses are read from a storage medium such as disk, drum, or tape using double-frequency modulation, the clock and data system can become skewed out of proper timing due to the magnetic surface recording phenomenon known as domain spreading. This tendency to skew is worsened when the information is packed on the storage medium very densely. Described is a logic circuit for sensing such skewing of the information which would otherwise result in an error. It corrects the errors and provides properly timed clock and data pulses on its outputs.

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Skew Detector and Corrector for a Disk, Drum, or Tape Storage

When clock and data pulses are read from a storage medium such as disk, drum, or tape using double-frequency modulation, the clock and data system can become skewed out of proper timing due to the magnetic surface recording phenomenon known as domain spreading. This tendency to skew is worsened when the information is packed on the storage medium very densely. Described is a logic circuit for sensing such skewing of the information which would otherwise result in an error. It corrects the errors and provides properly timed clock and data pulses on its outputs.

The described skew detector and corrector, operates to sense the normal clock pulses, early clock pulses, late clock pulses, and data pulses, and will compensate for those pulses that are skewed out of normal timing tolerances, by generating clock pulses at the proper time and inhibiting the early and late clock pulses. Following sensing of a late clock pulse, the data gate is inhibited completely so that neither late clock pulses nor early clock pulses will be detected as data. No data is present in the position, this being the reason for the skewed late clock.

Following a data bit, the data bit is delayed and used to generate an auxiliary clock pulse at the proper time, correctly starting another Pulse Repetition Time (PRT). Following a zero data bit with its following clock pulse being skewed early, the auxiliary clock pulse inserted at the proper timing is actually the previous clock pulse delayed one PRT.

The schematic in Fig. 6 shows the skew detector and correction logic circuit. The AND gates, OR gates, and Inverters are labeled A, OR, and N, respectively. The latches are named, and the two time delays are numbered. The waveforms noted at various points throughout the schematic have written with them their timing, in relation to the point in the PRT at which they turn on.

A clock pulse is either gated through A-1 and OR'd through OR-1 or one of the two auxiliary clock pulses is inserted through OR-1 to set the CLOCK latch. The leading edge of the CLOCK output is generated at the Q output. A negative leading edge at Q is time delayed 0.25 or 1/4 of a PRT and fed back to the CLOCK latch reset input to reset it, thus determining the output CLOCK width.

The clock gate, formed at A-1, is present except when either of three inhibit signals are present. Refer to the timing diagram of Fig. 1. The first inhibit to turn off A-1 is the negation of the data gate at 0.425 PRT. The delayed clock also goes negative on A-1's input at 0.575 PRT. This delayed clock toggles back positive (0.95 PRT) at a time prior to a nominal clock input to gate it through properly. The third inhibit into A-1 is the LATE CL0CK latch's Q. This latch sets to indicate that a late clock has been detected. If a late clock occurs, there is a phi data bit following that late clock; therefore, the forming of the data gate at A-2 is inhibited. Since...