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Browse Prior Art Database

Tester for Data Processing System

IP.com Disclosure Number: IPCOM000083575D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Giaccone, LF: AUTHOR

Abstract

The processor and the memory of the drawing are part of a data processing system that is to be tested by a program that runs on the processor. During the test, the processor supplies addresses to the memory on a memory address bus and instructions and data are transmitted between the processor and the memory on a data bus.

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Tester for Data Processing System

The processor and the memory of the drawing are part of a data processing system that is to be tested by a program that runs on the processor. During the test, the processor supplies addresses to the memory on a memory address bus and instructions and data are transmitted between the processor and the memory on a data bus.

In the operation of a test program it is desirable to detect when a particular instruction is fetched from the memory. The processor operation then shifts to an alternate program that helps test personnel understand a fault that may be occurring. For example, the alternate program may alter the contents of register or storage or display their contents. It may similarly modify or display the contents of a control space, or it may test the connections to the program.

These test operations are conventionally handled by programming. For example, the instruction that is to be monitored can be altered to have an invalid field, so that the normal operation of the program is halted and the alternate program begins operation. The test can be run under the control of a program that monitors each instruction of the test program, and takes the selected action when a particular instruction is fetched.

In the apparatus of the drawing, an address compare circuit is connected to the memory address bus to receive the addresses that are supplied to the memory. It also receives the address of the instruction that is to be monitor...