Browse Prior Art Database

Unlocked Sequence Generator

IP.com Disclosure Number: IPCOM000083583D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Rauf, CP: AUTHOR

Abstract

This circuit will generate clock pulses and a sequence of signals in response to the turning on of gate A.

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Unlocked Sequence Generator

This circuit will generate clock pulses and a sequence of signals in response to the turning on of gate A.

Since the output of the rightmost inverter I is positive, turning on gate A will cause the AND to have a positive output. The output of the AND will propagate through the inverters, until a negative output from the last inverter turns off the AND. The AND will continue to cycle on and off as long as gate A is on, generating clock signals B and C. The period of clock signals B and C will depend upon the delay introduced by the inverters.

Gate A being on will allow the first of a series of polarity hold latches PH to turn on when clock signal B becomes positive. The second PH will turn on when clock signal C becomes positive; the third PH will turn on when clock signal B again becomes positive; etc.

The PHs all have their reset lines connected to gate A so that they will be reset when gate A is turned off.

The circuit could function with a single inverter followed by a delay (with clock B connected directly to the output of the AND). However, the use of the string of inverters permits additional flexibility in controlling both the period (by selecting which (n+1)th inverter to feed back to the AND) and the phase relationship (by selecting the number of inverters) of clocks B and C.

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