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CPU Program Check for Virtual Memory

IP.com Disclosure Number: IPCOM000083621D
Original Publication Date: 1975-Jun-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Smith, HF: AUTHOR

Abstract

Some CPU's are architecturally arranged to react to a program check by storing away the address of the instruction causing the program check. It may be stored in a memory location pointed to by the interrupt level vector, for example in the IBM System/7. This fact may be employed to implement virtual memory address translation and paging. Specifically, program check interruptions due to invalid addresses (as at the end of a page) and invalid op-codes (as in a branch and link to another page) are used to indicate that either a translation of from virtual to real, or paging, is required.

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CPU Program Check for Virtual Memory

Some CPU's are architecturally arranged to react to a program check by storing away the address of the instruction causing the program check. It may be stored in a memory location pointed to by the interrupt level vector, for example in the IBM System/7. This fact may be employed to implement virtual memory address translation and paging. Specifically, program check interruptions due to invalid addresses (as at the end of a page) and invalid op-codes (as in a branch and link to another page) are used to indicate that either a translation of from virtual to real, or paging, is required.

If the cause is an invalid address, the instruction that caused the interruption is fetched and decoded, the invalid address is computed, it is translated to the corresponding real address, the instruction is simulated, and the machine status is updated as required.

If the cause is an invalid op-code related to this arrangement, the instruction that caused the interruption is fetched and decoded, the real address is translated to the corresponding virtual address, and the instruction is simulated. If the instruction is a branch and link with a virtual target address, then a translation is made to the real address. In either case, the machine status (register contents and condition indicators, possibly updated) is then restored and a branch is taken to the next instruction to be executed.

A further mechanism is arranged to also store the contents...