Browse Prior Art Database

Photocurrent Equalization

IP.com Disclosure Number: IPCOM000083649D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Engelbrecht, JC: AUTHOR [+2]

Abstract

In optical position sensing systems in which desired detent positions are defined by equal output signals from a pair of light-sensitive elements, positional errors may be introduced when the light-sensitive elements are not carefully matched, or when the peak intensity of light available to the light-sensitive elements is not the same at all elements.

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Photocurrent Equalization

In optical position sensing systems in which desired detent positions are defined by equal output signals from a pair of light-sensitive elements, positional errors may be introduced when the light-sensitive elements are not carefully matched, or when the peak intensity of light available to the light-sensitive elements is not the same at all elements.

Circuitry is provided in the above system for equalization of the characteristics of a pair of phototransistors utilized for sensing light from a pair of light-emitting diodes (LED's), to provide an indication of positional detents when it is not feasible to use matched pairs of light-emitting diodes and matched pairs of phototransistors.

Power supply voltage, V1, is applied to resistors R1 and R4 which are connected to light-emitting diodes LED1 and LED2, respectively. Illumination of LED1 and LED2 is sensed by phototransistors T1 and T4. The collectors of T1 and T4 are connected to power supply voltage, V2, and the emitters of T1 and T4 are connected through resistors R3 and R6, respectively, to ground.

As currents flow through T1 and T4 voltages VS1 and VS2 are present at nodes 12 and 14, respectively, and are applied to inputs of comparators 4 and 9, respectively. A reference voltage VREF is applied to second inputs of comparators 4 and 9. The outputs of comparators 4 and 9 are connected to inputs of AND's 15 and 16, respectively.

During system calibration the INHIBIT inputs to AND's 15 and 16 is driven posit...