Browse Prior Art Database

Making Four Quadrant Multiplying Digital Analog Converters

IP.com Disclosure Number: IPCOM000083651D
Original Publication Date: 1975-Jul-01
Included in the Prior Art Database: 2005-Mar-01
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Boinodiris, S: AUTHOR

Abstract

This is a technique by which two relatively inexpensive single-quadrant multipliers can be connected in a fashion where they can make a new circuit of a four-quadrant multiplying digital/analog converter (DAC). Since single-quadrant multiplying DACs are available in monolithic integrated circuit (IC) forms and are relatively inexpensive and easy to manufacture, a four-quadrant multiplying DAC can be designed utilizing these blocks.

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Making Four Quadrant Multiplying Digital Analog Converters

This is a technique by which two relatively inexpensive single-quadrant multipliers can be connected in a fashion where they can make a new circuit of a four-quadrant multiplying digital/analog converter (DAC). Since single-quadrant multiplying DACs are available in monolithic integrated circuit (IC) forms and are relatively inexpensive and easy to manufacture, a four-quadrant multiplying DAC can be designed utilizing these blocks.

The circuit consists of a DC offset addition to provide a one-quadrant input and a subsequent subtraction of the same DC offset by a current translator. A sign bit is also added simply through a single analog switch. An output amplifier provides a voltage output for the multiplier. The result can be mathematically explained by a variable x, less in amplitude than a positive quantity K and bidirectional in sign. Also by bipolar quantities Y & Z where Z = XY. Then Z can also be expressed by Z = (X + K) Y - KY, where K and (X + K) now are positive only.

Referring to Fig. 1, the four-quadrant multiplier consists of the following sections: a) An input unity gain, buffer amplifier A1, of preferably low offset voltage. b) A DC offset adder containing a voltage source VOFS of low-source impedance. The adder also contains a buffer amplifier A2 receiving an input from a divider composed of R1 and R2, and sending varying current through R3 to the input of M1. c) Two potentiometers for trimmed resistors during assembly RB and RS that trim for BALANCE and the SIGN bit. d) Two single-quadrant multiplying current DACS. Their analog input is a differential amplifier whose one input is referenced to ground. The output is of current output configuration. If the compliance is adequate, the section of A2, A4, Q3 of the current translator can be eliminated. If not adequate, the section must be there. e) A current translator with a compliance increasing circuit...